Integrated circuits are typically fabricated over a semiconductive substrate and can include many individual transistor or device constructions. Implementing electrical circuits involves connecting isolated devices through specific electrical paths. It must, therefore, be possible to isolate respective transistor or device constructions. A variety of techniques have been developed to isolate devices in integrated circuits. One technique, termed LOCOS isolation (for LOCal Oxidation of Silicon) involves the formation of a semi-recessed oxide in the nonactive (or field) areas of the substrate. Prior art LOCOS isolation is discussed briefly in this section as such pertains to the present invention. For a more detailed discussion of LOCOS isolation, the reader is directed to a text by Wolf entitled, "Silicon Processing for the VLSI Era", Vol. 2, Chapter 2, the disclosure of which is hereby incorporated by reference.
Referring to FIG. 1, a prior art semiconductor wafer fragment in process is indicated generally by reference numeral 10. Such comprises a semiconductive substrate 12 over which a field oxide or isolation oxide region is to be formed by LOCOS techniques. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to bulk semiconductive material such as semiconductive wafer (either alone or in assemblies comprising other materials thereon) and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. A pad oxide layer 14 is formed over substrate 12 and an oxidation mask 16, comprised of a suitable material such as silicon nitride, is formed over pad oxide layer 14. Portions of layers 14, 16 (not shown) have been removed to expose a substrate portion 18. Portion 18 constitutes a portion of the substrate in which a LOCOS isolation structure or isolation oxide region is to be formed. Adjacent substrate portion 18, a masked substrate portion 20 remains. Portion 20 constitutes at least a portion of the substrate which is to support at least one integrated circuit construction. Accordingly, such portion constitutes an active area.
Referring to FIG. 2, substrate 12 is exposed to oxidation conditions which are sufficient to form oxide isolation region or field oxide region 22 within portion 18. Accordingly, as is known, the formation of region 22 typically causes a bird's beak region 24 to be formed, a portion of which extends under and upwardly lifts oxidation mask 16.
Referring to FIG. 3, oxidation mask 16 and pad oxide layer 14 are suitably removed or etched. Such defines a more pronounced bird's beak in region 24.
Referring to FIG. 4, a sacrificial oxide layer 26 is formed over substrate 12 typically to overcome a phenomena known as the Kooi effect. During the growth of field oxide, the Kooi effect can cause later defects when a gate oxide is formed. More specifically, during field oxide growth, a thin layer of silicon nitride can form on the silicon surface and close to the border of the active regions as a result of the reaction between the oxidizing species, oxygen and water, and the silicon nitride. In particular, NH.sub.3 is generated from the reaction between the water and the masking nitride during the field oxidation step. This NH.sub.3 then diffuses through the oxide and reacts with the silicon substrate to form silicon-nitride ribbons. When the nitride mask and pad oxide are removed, there is a possibility that the silicon-nitride ribbon remains present. When gate oxide is subsequently grown, the growth rate becomes impeded at the locations where such silicon-nitride ribbons remain. The gate oxide is thus thinner at these locations than elsewhere giving rise to problems associated to low voltage breakdown of the gate oxide. The most widely used method of eliminating the silicon-nitride ribbon problem is to grow a sacrificial oxide layer, typically about 25 to about 50 nanometers thick, after stripping the masking nitride and pad oxide. This sacrificial oxide layer is then removed by wet etching before growing the final gate oxide.
It has been found that the removal of the prior formed pad oxide layer 14 (FIG. 2) together with the formation and removal of the sacrificial oxide layer 26 can lead to a slightly thinner region 28 adjacent oxide isolation region 22 when the gate oxide layer is ultimately formed.
Referring to FIG. 5, and prior to formation of a gate oxide layer, sacrificial oxide layer 26 is suitably removed. In the illustrated example, such can cause field oxide region 22 to be recessed to a degree which results in the formation of a convex bump 30 laterally adjacent oxide isolation region 22.
Referring to FIG. 6, a gate oxide layer 32 is formed over substrate 12. Oxidation of bump 30 results in localized thinning of the gate oxide within region 28. Such thinning can lead to device failure brought on by gate shorting.
This invention arose out of concerns associated with improving the processing of semiconductor devices. This invention also arose out of concerns associated with improving the uniformity with which semiconductor devices can be formed.